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HD74SSTV16859 1:2 13-bit sstl_2 registered buffer ade-205-337g (z) rev.7 june 2001 description the HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 v to 2.7 v vcc operation and lvcmos reset ( reset ) input / sstl_2 data (d) inputs and clk input. data flow from d to qa, qb is controlled by differential clock pins (clk, clk ) and the reset . data is triggered on the positive edge of the positive clock (clk), and the negative clock ( clk ) must be used to maintain noise margins. when reset is low, all registers are reset and all outputs are low. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. features ? supports lvcmos reset ( reset ) input / sstl_2 data (d) inputs and clk input ? differential sstl_2 (stub series terminated logic) clk signal ? flow through architecture optimizes pcb layout function table inputs outputs reset reset reset reset clk clk clk clk clk d qa qb l xxxll h hhh h lll h l or h h or l x q 0 *1 q 0 *1 h : high level l : low level x : immaterial : low to high transition : high to low transition note: 1. output level before the indicated steady state input conditions were established.
HD74SSTV16859 rev.7, june. 2001, page 2 of 14 pin arrangement (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d3 25 40 d2 26 39 gnd 27 38 28 37 d4 d5 gnd clk gnd clk rese t gnd d8 d7 d6 d9 d10 gnd d12 d11 gnd v cc v cc v ddq v ref v ddq v cc v ddq v ddq v ddq v ddq v ddq v ddq q12a q11a q10a q09a q08a gnd q07a q05a q06a q04a q03a q02a q01a q00a q12b gnd q10b q11b q08b q09b q07b q06b q05b gnd q04b q03b 29 36 d1 30 35 d0 q02b q01b 31 34 gnd 32 33 q00b
HD74SSTV16859 rev.7, june. 2001, page 3 of 14 absolute maximum ratings item symbol ratings unit conditions supply voltage v cc or v ddq ?0.5 to 3.6 v input voltage *1 v i ?0.5 to v ddq +0.5 v output voltage *1 v o ?0.5 to v ddq +0.5 v input clamp current i ik 50 ma v i < 0 or v i > v cc output clamp current i ok 50 ma v o < 0 or v o > v ddq continuous output current i o 50 ma v o = 0 to v ddq v cc , v ddq or gnd current / pin i cc , i ddq or i gnd 100 ma maximum power dissipation at ta = 55c (in still air) p t 1 w tssop storage temperature tstg ?65 to +150 c notes: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
HD74SSTV16859 rev.7, june. 2001, page 4 of 14 recommended operating conditions item symbol min typ max unit conditions supply voltage v cc v ddq 2.5 2.7 v output supply voltage v ddq 2.3 2.5 2.7 v reference voltage v ref 1.15 1.25 1.35 v v ref = 0.5 v ddq termination voltage v tt v ref ?40 mv v ref v ref +40 mv v input voltage v i 0?v cc v ac high level input voltage v ih v ref +310 mv ? ? v d ac low level input voltage v il ??v ref ?310 mv v d dc high level input voltage v ih v ref +150 mv ? ? v d dc low level input voltage v il ??v ref ?150 mv v d high level input voltage v ih 1.7 ? v ddq +0.3 v reset low level input voltage v il ?0.3 ? 0.7 v reset differential (common mode range) v cmr 0.97 ? 1.53 v clk, clk input voltage (minimum peak to peak input) v pp 360 ? ? mv clk, clk high level output current i oh ? ? ?20 ma low level output current i ol ??20 ma operating temperature ta 0 ? 70 c note: the reset input of the device must be held at v ddq or gnd to ensure proper device operation. the differential inputs must not be floating, unless reset is low.
HD74SSTV16859 rev.7, june. 2001, page 5 of 14 logic diagram c l k d 0 51 4 8 4 9 35 v ref 4 5 1 6 q 00 a c l k r e s e t * 1 r 1d c1 32 q 00 b to tw e lv e oth e r c h a nn e l s note: 1. reset input gate is connected to v ddq .
HD74SSTV16859 rev.7, june. 2001, page 6 of 14 electrical characteristics item symbol v cc (v) min typ max unit test conditions input diode voltage v ik 2.3 ? ? ?1.2 v i in = ?18 ma output voltage v oh 2.3 to 2.7 v cc ?0.2 ? ? v i oh = ?100 a 2.3 1.95 ? v ddq i oh = ?16 ma v ol 2.3 to 2.7 ? ? 0.2 i ol = 100 a 2.3 0 ? 0.35 i ol = 16 ma input current (all inputs) i in 2.7 ? ? 5 a v in = 2.7 v or 0 quiescent supply current i cc *2 2.7 ? ? 45 ma v in = v ih ( ac ) or v il ( ac ) , i o = 0 standby current i cc (stdy) 2.7 ? ? 10 a reset = gnd dynamic operating clock only i ccd *2 2.7 ? ? 90 a/ clock mhz reset = v cc , v i = v ih(ac) or v il(ac) , clk and clk switching 50% duty cycle dynamic operating per each data input i ccd *2 2.7 ? ? 20 a/ clock mhz/ data input reset = v cc , v i = v ih(ac) or v il(ac) , clk and clk switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. output high *3 r oh 2.3 to 2.7 7 ? 22 *4 ? i oh = ?20 ma output low *3 r ol 2.3 to 2.7 7 ? 22 *4 ? i ol = 20 ma ? r oh ? r ol ? each separate bit *3 r o( ? ) 2.5 ? ? 4 ? i o = 20 ma, ta = 25c input data inputs c in 2.5 *1 2.5 ? 3.5 pf v i = v ref 310 mv capacitance clk and clk 2.5 ? 3.5 v cmr = 1.25 v, v pp = 360 mv reset ?3.0? v i = v cc or gnd notes: 1. all typical values are at v cc = 2.5 v, ta = 25c. 2. total i cc (max) = i cc + {i ccd (clock) f(clock)} + {i ccd (data) 1/2f(clock) 13} 3. this is effective in the case that it did terminate by resistance. 4. see figure. 1, 2
HD74SSTV16859 rev.7, june. 2001, page 7 of 14 switching characteristics item symbol v cc = 2.5 0.2 v unit test condition min max clock frequency *1 f clock ? 200 mhz setup time fast slew rate *4, 6 t su 0.75 ? ns data before clk , clk slow slew rate *5, 6 0.9 ? hold time fast slew rate *4, 6 t h 0.75 ? ns data after clk , clk slow slew rate *5, 6 0.9 ? differential inputs active time t act 22 ? ns data inputs must be low after reset high. differential inputs inactive time t inact 22 ? ns data and clock inputs must be held at valid levels (not floating) after reset low. pulse width t w 2.5 ? ns clk , clk ?h? or ?l? output slew *3 t sl 1 4 volt/ns (c l = 30 pf, r l = 50 ? , v ref = v tt = v ddq 0.5) item symbol v cc = 2.5 0.2 v unit from to min typ max (input) (output) maximum clock frequency f max 200 ? ? mhz propagation delay time *2 t plh, t phl 1.1 ? 2.8 ns clk, clk qa, qb t phl ??5.0 reset qa, qb notes: 1. although the clock is differential, all timing is relative to clk going high and clk going low. 2. this timing relationship is specified into test load (see waveforms ? 3, 4) with all of the outputs switching. 3. assumes into an equivalent, distributed load to the address net structure defined in the application information provided in this specification. 4. for data signal input slew rate 1 v/ns. 5. for data signal input slew rate 0.5 v/ns and < 1 v/ns. 6. clk, clk signals input slew rates are 1 v/ns.
HD74SSTV16859 rev.7, june. 2001, page 8 of 14 test circuit c = 30 pf l test point v tt *1 *2 50 ? notes: 1. c l includes probe and jig capacitance. 2. v tt = v ref = v ddq 0.5 waveforms ? 1 lvcmos reset input v /2 cc v /2 cc 10 % *1 90 % v cc 0 v i cch i ccl i cc t inact t act
HD74SSTV16859 rev.7, june. 2001, page 9 of 14 waveforms ? 2 t su t h t w timing input input input v cmr v pp v ref v ref v ref v ref v ih v il v ih v il waveforms ? 3 timing input output v cmr v cmr v tt v tt v pp v oh v ol t plh t phl
HD74SSTV16859 rev.7, june. 2001, page 10 of 14 waveforms ? 4 lvcmos reset input output v /2 cc v ih v il v oh v ol v tt t phl notes: 1. i cc tested with clock and data inputs held at v cc or gnd, and i o = 0 ma. 2. all input pulses are supplied by generators having the following characteristics : prr 10 mhz, zo = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). 3. the outputs are measured one at a time with one transition per measurement. 4. v tt = v ref = v ddq /2 5. v ih = v ref +310 mv (ac voltage levels) for differential inputs. v ih = v cc for lvcmos input. 6. v il = v ref ?310 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 7. t plh and t phl are the same as t pd
HD74SSTV16859 rev.7, june. 2001, page 11 of 14 application data min voltage (v) ? pull-down current (amps) max 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 figure . 1 min voltage (v) current (amps) max 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -100 -80 -60 -40 -20 0 ? pull-up figure . 2
HD74SSTV16859 rev.7, june. 2001, page 12 of 14 curve data voltage (v) pull-down pull-up i (ma) i (ma) i (ma) i (ma) min max min max 0.0 0 0 0 0 0.1 6 7 ?5 ?7 0.2 10 15 ?10 ?13 0.3 15 22 ?15 ?19 0.4 19 29 ?19 ?25 0.5 23 35.5 ?23.5 ?31 0.6 27 41.5 ?28 ?37 0.7 30.5 48 ?31.5 ?42 0.8 34 54 ?35 ?47 0.9 36.5 59 ?38 ?53 1.0 38.5 65 ?41 ?58 1.1 40 70 ?44 ?62 1.2 42 75 ?46 ?66 1.3 43 79 ?48 ?71 1.4 44 82 ?50 ?74 1.5 44 84.5 ?51 ?77 1.6 45 87 ?52 ?81 1.7 45 89 ?52 ?84 1.8 45 90 ?52.5 ?86 1.9 45 90 ?53 ?89 2.0 45 91 ?53 ?91 2.1 46 91 ?53.5 ?92 2.2 46 91 ?54 ?93 2.3 46 91 ?54 ?94 2.4 46 91.5 ?54 ?95 2.5 46 92 ?54.5 ?96.5 2.6 46 92 ?55 ?98 2.7 46 92 ?55 ?99
HD74SSTV16859 rev.7, june. 2001, page 13 of 14 package dimensions unit : mm *pd plating hitachi code jedec eiaj weight (reference value) ttp-64d ? conforms 0.47 g 0.08 17.0 17.2 max 64 33 32 1 0.50 6.10 0.08 m *0.20 ?0.05 0.90 max 1.20 max *0.15 ?0.05 0.05 ?0.05 8.10 ?0.20 0? - 8? 0.5 ?0.1 1.0
HD74SSTV16859 rev.7, june. 2001, page 14 of 14 disclaimer 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi?s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi?s sales office for any questions regarding this document or hitachi semiconductor products. sales offices hitachi, ltd. semiconductor & integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright ? hitachi, ltd., 2001. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65>-538-6533/538-8577 fax : <65>-538-6933/538-3877 url : http://www.hitachi.com.sg url northamerica : http://semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia : http://sicapac.hitachi-asia.com japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886>-(2)-2718-3666 fax : <886>-(2)-2718-8180 telex : 23222 has-tp url : http://www.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852>-(2)-735-9218 fax : <852>-(2)-730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher stra e 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 585200 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: colophon 4.0

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